Xilinx Vivado 2020.2 [ 1080p · UHD ]

# Open synthesized design open_run synth_1 write_verilog -force ./outputs/post_synth_netlist.v write_vhdl -force ./outputs/post_synth_netlist.vhd Write DCP (design checkpoint) write_checkpoint -force ./outputs/post_synth.dcp Report utilization & timing report_utilization -file ./outputs/post_synth_util.rpt report_timing -file ./outputs/post_synth_timing.rpt 2. Post-Implementation (Place & Route) After implementation (place & route):

Then in simulation (Questa/Modelsim/XSIM): xilinx vivado 2020.2

# From implemented design write_verilog -mode timesim -sdf_anno true -file ./outputs/post_route_sim.v write_sdf -file ./outputs/design.sdf xilinx vivado 2020.2